Method and apparatus for efficient performance monitoring of a large number of simultaneous events

ABSTRACT

A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application relates to commonly-owned, co-pending U.S.patent applications Ser. No. ______ [Docket No. 19829; YOR920060335US1];Ser. No. ______ [Docket No. 19830; YOR9200600336US1] and, Ser. No.______ [Docket No. 19831; YOR920060337US1], each of which was filed oneven date herewith.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to computer systems using singleor multiprocessor architectures and, more particularly, to a novelimplementation of performance counters for recording occurrence ofcertain events. In even more particular aspect, this invention relatesto a performance monitoring system for more efficiently managing thecounting of large number of individual events in a computer system byproviding a hybrid counter array device for counting events withinterrupt indication.

2. Description of the Prior Art

Many processor architectures include on a chip a set of counters thatallow counting a series of processor events and system events on thechip, such as cache misses, pipeline stalls and floating pointoperations. This counter block is referred to as “performance counters”.

Performance counters are used for monitoring system components such asprocessors, memory, and network I/O. Statistics of processor events canbe collected in hardware with little or no overhead from operatingsystem and application running on it, making these counters a powerfulmeans to monitor an application and analyze its performance. Suchcounters do not require recompilation of applications.

Performance counters are important for evaluating performance of acomputer system. This is particularly important for high-performancecomputing systems, such as BlueGene/P, where performance tuning toachieve high efficiency on a highly parallel system is critical.Performance counters provide highly important feedback mechanism to theapplication tuning specialists.

Many processors available, such as UltraSPARC and Pentium provideperformance counters. However, most traditional processors support avery limited number of counters. For example, Intel's X86 and IBMPowerPC implementations typically support 4 to 8 event counters. Whiletypically each counter can be programmed to count specific event fromthe set of possible counter events, it is not possible to count morethan N events simultaneously, where N is the number of countersphysically implemented on the chip. If an application tuning specialistneeds to collect information on more than N processor, memory or I/Oevents, he has to repeat execution of the application several times,each time with different setting of performance counters.

While this is time consuming, the collected statistics can also beinaccurate, as various application runs can have different set ofevents, because of different conditions such as initial condition ofmemory, preloaded caches, etc. This is especially true formultiprocessor applications.

The main reason for not including a large number of counters on aprocessor chips is that their implementations are large in area andcause high-power dissipation. Frequently, not only large number ofcounters is needed, but also the counters have to be large themselves(for example, having 64 bits per counter) to avoid overflowing andwrapping around during the application run.

It would be highly desirable to have an implementation of event counterswhich is able to support a large number of tracked eventssimultaneously, which is compact in area and having low power. This isespecially important for systems on a single chip with limited area andpower budget.

A reference entitled “Maintaining statistics counters in router linecards” published in IEEE Micro 2002 by D. Shah, S. Iyer, B. Prabhakar,and N. McKeown describe implementation of large counter array fornetwork routers. The counters are implemented using SRAM memory forstoring m lower counter bits for N counters, and DRAM memory for storingN counters of width M, and m<M. The SRAM counters track the number ofupdates not yet reflected in the DRAM counters. Periodically, DRAMcounters are updated by adding the values in the SRAM counters to theDRAM counters, as shown in FIG. 1. This implementation limits the speedof events which can be recorded to be at most the speed of updating SRAMmemory. Whereas this is sufficient for tracking network traffic, thisimplementation is too slow to be useful for processor performancecounters. Also, while network traffic is necessarily serial—limited by acommunication line—multiple events occur in pipelined processorarchitecture simultaneously every cycle, making this implementationinappropriate for processor system performance counters.

In the prior art, the following patents address related subject matterto the present invention, as follows:

U.S. Pat. No. 5,615,135 describes implementation of a reconfigurablecounter array. The counter array can be configured into counters ofdifferent sizes, and can be configured into groups of counters. Thisinvention does not teach or suggest a system and method for using SRAMfor implementing counter arrays.

U.S. Pat. No. 5,687,173 describes an implementation of a counter arrayuseful for network switches. The implementation employs a register arrayfor implementing large number of event counters. This invention does notteach or suggest a system and method for using SRAM for implementingcounter arrays. SRAM based implementation for counter arrays of the samesize is of higher density and lower power dissipation, compared toregister array based counter implementation. Additionally, registerarray based implementation with N registers can update at most ncounters simultaneously, with n being number of write ports to theregister array, and n<<N. This makes register array based counter arrayimplementation unsuitable for processor system performance counters.

U.S. Pat. No. 6,567,340 B1 describes an implementation of counters usingmemory cells. This invention teaches usage of memory cells for buildinglatches. These latches with embedded memory cells can than be used forbuilding counters and counters arrays. This patent does not teach orsuggest a system and method for using SRAM or DRAM memory arrays forimplementing counter arrays.

U.S. Pat. No. US 6,658,584 describes implementation of large counterarrays by storing inactive values in memory, and referencing the propercounters by employing tables. On a counter event, the table isreferenced to identify the memory location of the selected counter, andthe counter value is read from the memory location, updated and storedback. The access to counters is managed by bunk of several processors,which identify events, and counter manager circuitry, which updatesselected counters. This patent does not teach hybrid implementation ofcounters using latches and memory arrays, and has too low latency to beable to keep up with monitoring simultaneous events in a singleprocessor.

U.S. Patent Application No. US 2005/0262333 A1 describes animplementation of branch prediction unit which uses array to store howmany loop iterations each loop is going to be executed to improvesbranch prediction rate. It does not teach how to implement countersusing both latches and memory arrays.

None of the prior art provides a solution to the problem of implementinga large number of high-speed counters able to track eventssimultaneously, which is compact in area and with low power.

It would thus be highly desirable to provide a simple and efficienthardware device and methodology for counting simultaneously large numberof individual events in a single or multiprocessor computer system.

SUMMARY OF THE INVENTION

A novel implementation of large counter arrays for countingsimultaneously large number of individual events in a single ormultiprocessor system is provided. The invention teaches a counter arrayimplementation that is compact in area, and is a low powerimplementation that scales well with high number of simultaneouslycounted events. The invention teaches implementation of counter array byusing both latches and memory arrays for implementing large number oflarge counters. In this hybrid counter implementation, a number of nleast significant bits of a counter are implemented using discreteregisters, whereas the N-n most significant bits of counters are storedin a memory array, where N is the number of bits in a counter.

More particularly, a method and apparatus is provided for effectivelyreducing the area required to implement large array of large counters byusing a memory array, such as SRAM or DRAM arrays for implementinghigher bits of large counters, and by using latches to implement lowerbits of counters. Updating of the memory array is performedperiodically, and is controlled by a state machine. The counter array inthe present invention is significantly smaller than a discrete-registerbased counter array implementation. Reducing the area requirements forevent counter arrays in a single or multiprocessor system enablestracking of much larger number of events with reduced power. Largenumber of event statistics is then used to tune applications to increaseapplication performance and ultimately, system performance. Performancecounters provide highly important feedback mechanism to the applicationtuning specialists. This is particularly important for high-performancecomputing systems, where applications are carefully tuned to achievehigh efficiency on a highly parallel system.

Furthermore, the novel implementation of large counter arrays forcounting simultaneously large number of individual events is enabled byassigning one or more configuration bits to each respective counterdevice for defining a mode of operation of the counter device. One modeof operation comprises an interrupt indication mode enablingpre-identification of possible interrupts to occur. That is, apre-identification status with the indicator flag associated with eachregister is stored such that an interrupt signal will be set as soon thelower bits of a counter have a “roll over” bit set for a counter havinga paired “interrupt arm” bit that is set, independently of the state ofa control state machine. This potentially saves hundreds of cycles asthe state machine needs to cycle thru all the counters of the hybridcounter array.

Further, the novel implementation of large counter arrays for countingsimultaneously large number of individual events implements a novelapproach for communicating data from a data bus to a wide data storagearray device, wherein the bus is of a narrow data (bit) width ascompared to the data (bit) width of the array to which data is to betransferred.

Thus, in accordance with the invention, there is provided: a system andmethod for monitoring performance of simultaneous occurring events in asingle or multiprocessor computer system, the system comprising:

a hybrid counter array means for counting signals representingoccurrences of events received from event sources having a first counterportion including one or more counter devices and providing a firstcount value corresponding to lower order bits of a count, and a secondcounter portion comprising a memory array device having addressablememory locations, each the addressable memory location for storing asecond count value for a respective counter device representing higherorder bits of the count, a combination of the first and correspondingsecond count values provide a number of events received at a counterdevice; and,

an interrupt pre-indication means for providing fast interrupt triggerto a processor device when one or more count values related to an eventequals a pre-determined threshold value,

a means enabling one or more of: read access or write access to both thefirst count value in the first counter portion and the second countvalue in the second counter portion, the read/write access for purposesof initializing and determining status of the count values for amonitored event type in response to a processor device request.

In the monitoring system of the invention, the means enabling one ormore of: read access or write access further comprises: a bus interfacemeans for enabling communication of the lower order bits and higherorder bits to and from respective the first counter portion and secondcounter portion of the hybrid counter array means. The bus interfacemeans includes a data bus device of bus width narrower than a bit widthof the count value provided as a combination of the first and the secondcounter portions.

Furthermore, in the monitoring system of the invention, the firstcounter portion of the hybrid counter array means comprises N counterdevices, the hybrid counter array means further comprising:

an overflow bit means associated with each respective N counter device,the overflow bit means being set in response to reaching overflowcondition;

a control means operatively coupled with each the N associated overflowbit means for monitoring each of the N associated overflow bit means ofthe first counter portion and initiating incrementing a value of acorresponding the second count value stored at the correspondingaddressable memory location in the second counter portion in response toa respective overflow bit being set, wherein after the initiating, theoverflow bit means being reset.

Furthermore, in the monitoring system of the invention, each counterdevice of the hybrid counter array device preferably comprises adiscrete element such as an incrementable register device. Preferably,the memory array device comprises one or more of: an SRAM, a DRAM orembedded DRAM.

Further, in the monitoring system of the invention, in oneimplementation of the hybrid counter array device, the control meanscomprises a finite state machine that monitors all N counter devices ina cycle.

Further to the hybrid counter array device for counting events withinterrupt indication, there is provided, in one embodiment:

an interrupt arming device associated with each respective N counterdevice for enabling fast interrupt indication, the interrupt armingdevice being set in response to the incremented second count value beingequal to a pre-determined threshold value; and,

a means implementing logic coupled to an output of the interrupt armingdevice and an output of the overflow bit means for asserting aninterrupt signal when an overflow bit means corresponding to a counterdevice is set and the interrupt arming device associated with thecounter device is set,

wherein the interrupt signal is asserted independent of a state of thecontrol means.

Further, in the monitoring system of the invention, the means forenabling write access to a wide count value provided as a combination ofthe first and the second counter portions via the narrow bit width databus comprises:

a means for generating select control signals for controlling writeaccess to a memory location of the memory array device and to a counterdevice in response to a processor device request;

a means for storing a predetermined number of bits of data communicatedvia the narrow bit width data bus corresponding to the first counterportion to be stored at the selected counter device; and

a means for storing a predetermined number of bits of data communicatedvia the narrow bit width data bus corresponding to the second counterportion to be stored at the selected addressable memory location of thememory array device.

Alternately, the means for enabling write access to a wide count valueprovided as a combination of the first and the second counter portionsvia the narrow bit width data bus comprises:

a means for generating select control signals for controlling writeaccess to a memory location of the memory array device and to a counterdevice in response to a processor device request;

a first staging device for receiving and storing a first predeterminednumber of bits of data to be stored at the selected hybrid countercommunicated via the data bus in a first write bus transaction;

a means for merging the first predetermined number of bits of data inthe first staging device with a second predetermined number of bits ofdata comprising a remaining portion of the data to be stored at theselected hybrid counter via the narrow bit width data bus beingcommunicated in a second write bus transaction; and

a means for storing a predetermined number of bits of merged datacorresponding to the first counter portion at the selected counterdevice, and storing a predetermined number of bits of merged datacorresponding to the second counter portion to selected addressablememory location of the memory array device, wherein the write access tothe hybrid counter is atomic.

Further, in the monitoring system of the invention, the means forenabling read access to a wide count value provided as a combination ofthe first and the second counter portions via the narrow bit width databus comprises:

a means for generating select control signals for controlling readaccess to a memory location of the memory array device and to a counterdevice in response to a processor device request;

a means for reading a predetermined number of bits of data from theselected counter device corresponding to the first counter portion, anddriving data to the data bus; and

a means for reading a predetermined number of bits of data from theselected addressable memory location of the memory array devicecorresponding to the second counter portion, and driving data to thedata bus.

Alternately, the means for enabling read access to wide count valueprovided as a combination of the first and the second counter portionsvia the narrow bit width data bus comprises:

a means for generating select control signals for controlling readaccess to a memory location of the memory array device and to a counterdevice in response to a processor device request;

a second staging device for receiving and storing a first predeterminednumber of bits of data read from the selected addressable memorylocation of the memory array device, the receiving and storing performedin a first read bus transaction;

a means for merging data corresponding to the first counter portion atthe selected counter device with the second predetermined number of bitsof data read from the selected addressable memory location of the memoryarray device, and driving data to the narrow bit width data bus inresponse to processor device request in a first read bus transaction;and

a means for driving data stored in the second staging register to thenarrow bit width data bus in a second read bus transaction, comprising aremaining portion of the data from the selected hybrid counter.

Preferably, the first and second staging devices comprise a registerdevice addressable by a processor device.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the present invention willbecome apparent to one skilled in the art, in view of the followingdetailed description taken in combination with the attached drawings, inwhich:

FIG. 1 depicts a counter array implementation according to the prior artusing SRAM memory for storing m lower counter bits for N counters, andDRAM memory for storing N counters of width M, and m<M Periodically,DRAM counters are updated by adding the values in the SRAM counters tothe DRAM counters;

FIG. 2 depicts on example embodiment of this invention, where 12 leastsignificant bits of a counter are implemented using discrete registers,and a remaining 52 most significant bits of counters are stored in aSRAM memory array;

FIG. 3 depicts a flow chart for updating the highest significant bits ofhybrid counters located in a memory array in accordance with a preferredembodiment of the invention;

FIG. 4 depicts a high level schematic of a hybrid counter implementationwith added support for interrupt indication in accordance with apreferred embodiment of the invention;

FIG. 5 is a block diagram depicting the hybrid counter arrayimplementation with interrupt pre-indication according to the presentinvention;

FIG. 6 is a flow chart depicting the control flow for early interruptindication for hybrid counter array implementation according to thepresent invention;

FIG. 7 depicts the control flow process for enabling one or moreprocessors in a single- or multi-processor system to access countervalues, in order to read, write or reset the counters of the counterunit;

FIG. 8 depicts a high level block diagram of a wide memory arrayimplementation with support for memory accesses via a narrow bus inaccordance with the present invention with FIG. 8A depicting a memorywrite operation, and FIG. 8B depicting a memory read operation;

FIGS. 9A and 9B depict methods implemented in hardware for respectivelywriting and reading data elements of a memory array according to theinvention;

FIGS. 10A, 10B, and 10C, depict methods implemented in software forrespectively writing data elements, reading data elements, andperforming a read-modify-write cycle on data elements of a memory arrayaccording to the invention; and,

FIG. 11 depicts an apparatus 1000 including the hybrid counter unit ofthe invention as a combination of the individual system components asdepicted in FIGS. 2, 4, 5 and 8A and 8B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to drawings, and more particularly to FIG. 2, there isdepicted the preferred embodiment of the invention. The performancecounter unit 100 includes N counter devices. The N counter events tomonitor are selected from set of M events selected by the set of Nmultiplexers 110. The selected performance events are counted in thecounter block 120, which implements N counters which are n widthrepresenting n least significant bits of a counter. The counters in theblock 120 are implemented using discrete registers. In the preferredembodiment, the block 120 implements only lowest 12 bits of 64-bitcounters, but it is known to skilled artisans that any number of lowerbits can be counted in the discrete register logic block.

When a counter from the counter block 120 reaches its maximum, its valuerolls over to zero, and the corresponding bit in the “roll over bit”block 130 is set, and the counter continues to track performance events.

The K-n most significant bits of counters are stored in a memory arrayblock 140, where K is the number of bits in a counter. Thus, thedimensions of the memory array block 140 is N×(K-n) bits. The size ofthe memory array will be increased for additional bits needed if itimplements parity protection scheme, or ECC memory protection. In theillustrated embodiment, to implement 64-bit wide counters, the memoryarray contains 52 most significant bits, whereas the 12 leastsignificant bits are stored in the counters using discrete logic.

In the preferred embodiment, the memory array 140 is implemented usingSRAM memory array. It is understood that one skilled in the art mayimplement memory array using DRAM memory array, or some other memoryarray without departing from the scope of the invention.

It is to be understood, in yet another embodiment, that instead of usingone memory array block to implement all higher significance bits of thecounter arrays, multiple memory arrays can be used without departingfrom the scope of the invention. In a multiple array embodiment, counterbits can be split vertically across multiple memory arrays (so that mlbits are contained in the memory array M1, m2 bits are contained in thememory array M2, etc.), horizontally across multiple memory arrays (thusthe first n1 counters are contained in the memory block N1, the next n2counters are contained in the memory block N2, etc.), or somecombination of the two.

In yet another embodiment, hierarchical arrangement of multiple memoryarrays using different types of memory arrays can be used withoutdeparting from the scope of this invention. In the example embodiment,the lowest n1 bits of the counters can be implemented using discretelogic, the next n2 bits can be implemented using low latency memoryarray like SRAM, and the next n3 bits using the longer latency memoryarray like DRAM, etc.

It is to be understood that in yet another embodiment all combinationsdescribed above can be used simultaneously, i.e., hierarchical multiplememory block arrangement, and horizontal and vertical splitting ofcounter bits and counters across multiple memory blocks, withoutdeparting from the scope of the invention.

Referring back to FIG. 2, controlled by the control unit 160, eachmemory elements is accessed and—if the “roll over bit” associated tothat counter is set, this memory element is incremented in the incrementblock 150, and the incremented counter value is stored back to thememory array.

In the preferred embodiment, the control unit is implemented as a simplefinite state machine, which cycles through all N counters, from 0 to N−1in a loop. For each counter, the “roll over bit” is checked, and if thisbit is set, the paired counter value is fetched from the memory array140, incremented in the increment unit 150, and stored back to thememory array, whereas the “roll over bit” is cleared.

In yet another embodiment, the control unit implements some othercounter selection scheme to select counter from the memory array forupdating counter value without departing from the scope of thisinvention.

Referring now to FIG. 3, the flow chart depicts the control flow forupdating the most significant part of a hybrid counter located in thesaid memory array. At the start of operation at step 200 the variable iloop counter is set to zero as indicated at step 210. Then, for eachcounter is checked if the “roll over” bit is set. This is done one at atime, by checking the value of the “roll over” bit of the counter i, forthe current variable i, at step 220.

If the ‘roll over’ bit of the counter i is set, the memory arraycorresponding to i-th counter is loaded in the increment register, asindicated at step 230. Also in this step, the “roll over” bit of thei-th counter is cleared. The variable i is used to address thecorresponding memory location. At step 240, the value loaded in theincrement register is incremented, and at step 250 the new value fromthe increment register is stored back to the memory locationcorresponding to the i-th counter, addressed by the variable i.

If the ‘roll over’ bit of the counter i is not set—as determined at step220—, the execution proceeds to step 260, to increment the variable iand check the next counter.

The execution continues by incrementing the loop variable i at step 260,and checking if all N counters have been addressed at step 270. If all Ncounters have already been addressed, the loop variable i is reset tozero at step 210. If not all counters have been checked for roll overbit, the operation from steps 220-260 is repeated for the next counter.

In the preferred embodiment, the value of the i-th counter isincremented at step 240. In yet another embodiment, this value can bedecremented, or some value different than one can be added or subtractedfrom the counter without departing from the scope of the invention.

In the preferred embodiment, if the “roll over” bit is not set, thecontrol continues from the step 220 to 260 directly. In yet anotherembodiment, the control can go true one or more “idle” steps, so thatthe number of cycles spent in one iteration of the control loop is thesame for a counter which updates its value to a counter where no updatesare needed, without departing from the scope of this invention.

Referring now to FIG. 4, there is depicted a high level block diagramfor the hybrid counter implementation with added support for interruptindication in accordance with a preferred embodiment of the invention.In addition to the said components of the counter 310-360, one interruptthreshold register 370 and the comparison logic 380 is added. Thisinterrupt threshold register is set to desired value by using writeinterface from one or more processors to set it to predefined value.

The interrupt indication operates as follows: for each counter, if thecorresponding “roll over” bit is set, the counter value is retrieved outof the memory array in the increment register 350. The register value350 is incremented, and the resulting value is stored back to the memoryarray. In parallel, the incremented counter value in the incrementregister 350 is compared to the interrupt threshold value stored in theinterrupt threshold register 370 by the comparison logic 380. If thesetwo values are identical, the “interrupt” signal is set, otherwise, itremains zero.

In the preferred embodiment, only one interrupt threshold registerhaving the same number of bits as the most significant part of thecounter stored in the memory is used for interrupt generation of allcounters in the array. In yet another embodiment, a group of two or moreregisters for holding multiple interrupt values is used for checking theinterrupt condition, without departing from the scope of this invention.In the extreme case, the number of these registers equals to the numberof counters, thus every counter has assigned one threshold register. Inthe case of multiple registers with threshold values, each counter isconfigurable to select one of the interrupt threshold registers.

In yet another embodiment, set of threshold registers has paired a setof registers for storing addresses of counters it is paired to. Thus,one threshold register can have assigned one or more registers to storeone or more addresses i of assigned counters. In this embodiment, if thecounter address matches an address i stored in an address register j,the value in the increment register is compared to the threshold valuestored in the corresponding threshold register j. Other mappings ofthreshold registers to counters are also possible without departing fromthe scope of this invention.

In the preferred embodiment, the interrupt threshold register having thesame number of bits as the most significant part of the counter storedin the memory is used for interrupt generating. In yet anotherembodiment, the number of bits in the interrupt threshold equals to thenumber of bits in a counter (sum of the number of bits stored in thememory and the number of bits implemented as discrete logic) and beingcompared to the integral value of a counter, combining the bits of thecounter stored in the memory array with the bits stored in discreteregister to determine if the interrupt condition is met, withoutdeparting from the scope of the invention. In yet another embodiment,any subset of bits of an integral counter value is used for determiningif counter value equals the value of the threshold register, withoutdeparting from the scope of the invention.

The preferred embodiment for implementing area efficient counter arrayuses state machine, a memory array for storing most significant counterbits, and discrete registers for storing least significant bits ofcounter values. The preferred implementation updates the memory arrayportion of counters under control of a state machine. Thus, updating ofmemory array portion of counters is performed periodically.

If support for interrupt indication in a case when a counter reachespredefined threshold value is implemented, the comparison of a countervalue to the threshold value will also occur only periodically. As aresult, a counter comparison to a threshold value can be only performedwhen the full value of the counter register is available, that is whenthe memory array is being updated. This can lead to a long delay ofevent indication, which can be as long as being 2^(n) events late, wheren is the number of bits held in the register portion of a counter.

To overcome this problem, the present invention describes method andapparatus for hardware device which implements pre-identification ofpossible interrupts to occur during the next 2^(n) events, where n isthe number of bits held in the register portion of a counter, before thememory array is being updated. This is accomplished by storingpre-identification status with the indicator flag associated with eachregister, and as will be described below.

Referring now to FIG. 5, there is depicted a high level block diagram ofhybrid counter array implementation with interrupt pre-indicationaccording to the present invention. In the preferred embodiment, thehybrid counter array comprises: a set of input multiplexers 490, toselect set of events to be counted, a set of N counters being wide nbits, and being implemented using discrete registers logic 480, a memoryarray 410, having at least N memory locations at least K-n bits wide,where K is the number of bits in a single counter, a state machine 400for controlling periodical updates of the memory array 410, a set of“roll over” bits 485 for capturing events that a paired counter partimplemented as discrete registers had wrapped around, an incrementregister 420 to increment the value of the counter part stored in thememory array 410, an interrupt threshold register 430, to store thethreshold value, a comparison logic 440, which identifies that theincremented counter value in the increment register equals to the valuestored in the interrupt threshold register, a set of “interrupt arm”bits 450, a set of AND-gates 460, and an OR gate 470.

The invention operates as follows: to each of N counters is associatedan “interrupt arm” bit 450, to enable fast interrupts, and a “roll-over”bit 485, which is set when n-bit lower part of a counter reaches themaximum value and rolls back to zero. The state machine 400 controls theoperation of the counter unit 100, cycling thru all N counters. For eachselected counter, if the “roll-over” bit is set, high counter bits ofthe counter are pulled out of the memory array, incremented, and storedback to the memory array.

High order counter bits pulled out of memory array in the incrementregister 420 are compared to the interrupt threshold register 430. Inthe early interrupt indication mode, the counter value is compared tothe interrupt threshold value decremented by 1. If the interruptthreshold register decremented by one match the high order bits of thecounter, the corresponding “interrupt arm” bit 450 is set. After this,the “roll-over” bit 485 is set to zero, and the next counter isselected.

Setting “interrupt arm” bit enables fast interrupt indication. This bitis set for each counter if it matches the value stored in the thresholdregister decremented by one. Thus, setting the bits 450 is early warningthat on the next roll-over of the lower bits of a counter, the interruptwill be fired. Firing the interrupt is accomplished by AND-ing the“interrupt arm” bits 460 with the “roll over” bits 485 for each counter.If any one of the N counters from the counter array has both “interruptarm” bits and “roll over’ bits set, the corresponding signal value willbe one after going true the AND gates array 450, and reduced by globalOR-reduce 470, firing the interrupt. It is to be noted that theinterrupt signal will be set as soon the lower bits of a counter havethe “roll over” bit set for a counter whose paired “interrupt arm” bitis set, independently of the state of the control state machine 400.This potentially saves hundreds of cycles as the state machine needs tocycle thru all the counters. The single interrupt is fast if it is onthe boundary of 2^(n) which is where the lower n bits will roll over.

In yet another embodiment, a set of registers for “interrupt arm”indication may store the counter indication i which triggered earlyinterrupt indication. This implementation is preferable if a very largenumber of counters is present, as the number of storage elements willscale with the number of simultaneous pre-armed events supported, notwith the number of total counters. Other indication schemes are alsopossible, without departing from the scope of this invention.

Referring now to FIG. 6, the flow chart depicts the control flow forearly interrupt indication for hybrid counter array implementationaccording to the present invention. At the start of operation at step500 the variable i loop counter is set to zero as indicated at step 510.Then, for each counter is checked if the “roll over” bit is set. This isdone one at a time, by checking the value of the “roll over” bit of thecounter i, for the current variable i, at step 520.

If the ‘roll over’ bit of the counter i is not set—as determined at step520—, the execution proceeds to step 580, to increment the variable iand check the next counter.

If the “roll over’ bit of the counter i is set, the memory arraycorresponding to i-th counter is loaded in the increment register, asindicated at step 530. Also in this step, the “roll over” bit, and the“interrupt arm” bit of the i-th counter are cleared. The variable i isused to address the corresponding memory location. At step 540, thevalue loaded in the increment register is incremented.

At step 550, the value in the increment register is checked if it isequal to value of the threshold register decremented by one. If this isthe case, the control continues to step 560, where the paired “interruptarm” bit of the i-th counter is set. For this counter, an interrupt willbe fired next time the “roll over” bit of the i-th counter is set. Atstep 570 the new value from the increment register is stored back to thememory location corresponding to the i-th counter, addressed by thevariable i.

If at step 550, the value in the increment register does not equal tovalue of the threshold register decremented by one, the controlcontinues to step 570, where the new value from the increment registeris stored back to the memory location.

The execution continues by incrementing the loop variable i at step 580,and checking if all N counters have been addressed at step 590. If all Ncounters have already been addressed, the loop variable i is reset tozero at step 510. If not all counters have been checked for roll overbit, the operations from steps 520-580 are repeated for the nextcounter.

It is to be noted that, in addition to “interrupt arm” bit, each countercan have one or more assigned configuration bits to define the mode ofoperation of the counter, to select one from plurality of input events,and to enable or disable interrupts. In this embodiment, an interruptsignal will be raised only in the case where “interrupt enable”configuration bits are set, and the “interrupt arm” and “roll over” bitsare set. In the case that interrupt is not enabled, the interrupt signalwill not be set.

It is desirable to read, write or reset the counters of a counter unit.This is accomplished by adding additional actions to the control statemachine. To avoid the need for a second memory port (and therebysignificantly increasing the size of the storage array), processorrequests must be synchronized with rollover bit handling. This isachieved by testing for pending processor memory requests periodically.In the preferred embodiment, pending read- and write requests to thecounters are performed on each counter update, once per counter updatecycle independently if the counter is updated or not. In yet anotherembodiment, the counter update phase can be implemented with lowerfrequency, once every J, J>1 update cycles, or once for the whole cyclefor updating all N counters, without departing from the scope of theinvention.

Referring now to FIG. 7, there is depicted the control flow process forenabling to one or more processors in a single- or multi-processorsystem to access counter values, in order to read, write or reset thecounters of the counter unit. It is desirable that one or moreprocessors can read counter values, or to set counter values to somepre-defined value. At the start of operation at step 600 the variable iloop counter is set to zero as indicated at step 610. Then, for eachcounter is checked if the “roll over” bit is set. This is done one at atime, by checking the value of the “roll over” bit of the counter i, forthe current variable i, at step 620.

If the “roll over’ bit of the counter i is set, the memory arraycorresponding to i-th counter is loaded in the increment register, asindicated at step 630. Also in this step, the “roll over” bit of thei-th counter is cleared. The value loaded in the increment register isincremented in step 640, and at step 650 the new value from theincrement register is stored back to the memory location correspondingto the i-th counter.

Returning back to step 620, if the ‘roll over’ bit of the counter i isnot set, the execution proceeds to step 660, to check if there is anymemory requests from the processor pending. At step 660, the check ismade if one of the processor has issued read or write command to any ofthe counters in the counter array. If a memory request is pending, theCPU read- or write access to a counter j is handled in step 670, and thecontrol continues to step 680. If no processor read- or write access ispending, the control continues to step 680.

To retrieve value form any of hybrid counters to a processor, the bothparts of the counter have to be retrieved and assembled: the leastsignificant part of the counter stored in discrete registers, and themore significant part of the counter stored in the memory array. Onlyafter both parts of the counter have been retrieved, the counter valuecan be returned to the requesting processor. Similarly, on a counterwrite, the written data are split into two parts: the least significantpart to be stored in the discrete registers of the counter, and the mostsignificant part of the counter value to be stored in the memory array.

While the part of a counter stored in discrete latches can be retrievedimmediately, the value stored in the memory array can be accessed onlyat this step 670. Thus, the counter value retrieved from the memory andassembled with the part stored in the discrete register can be returnedto the requesting processor only after the step 670 for memory access isfinished, independently from the cycle in which the request wasreceived. Similarly, any value to be written in a counter has to bestored temporally in a register until the control state machine reachesthe state 670 to handle memory access.

The execution continues by incrementing the loop variable i at step 680,and checking if all N counters have been addressed at step 690. If all Ncounters have already been addressed, the loop variable i is cleared atstep 610. If not all N counters have been checked for roll over bit, theoperation from steps 620-670 is repeated for the next counter.

The CPU interface can be implemented over a variety of architected buswidths. When interfacing a counter unit with counters being 64 bitswidth with a bus having 64 bits or more, a single access can read orwrite a single event counter in one bus transaction.

For a write access, following actions are performed:

-   -   lower 12 bits of a write word are written into the 12 least        significant bits of a counter which are implemented as discrete        registers—performed immediately,    -   higher 52 bits are written into the SRAM memory array—performed        only when the state machine is in the “handle CPU read/write        request” state (state 670 in FIG. 7).

Until this state is reached, the word to be written is placed in astaging local register.

For a read access, following actions are performed:

-   -   higher 52 bits are read out of the SRAM memory array—performed        only when the state machine is in the “handle CPU read/write        request” state (state 670 in FIG. 7),    -   lower 12 bits are read out of the 12 least significant bits of a        counter which are implemented as discrete registers—performed        simultaneously with the memory read.

When interfacing the counter unit with counters being 64 bits width witha bus with less than 64 bits, a read- or write-access to event countersin the counter unit cannot be performed in one bus transaction. Such ascenario happens if a bus is being architected to only supporttransactions of a certain bit width less than 64 bits, or if a bus isarchitected as a wide 64 bit bus, but a counter value is requested by abus master which supports only narrow transactions.

Specifically, for a 64 bit counter unit and 32 bit bus transactions, aread cannot return the entire 64 bit counter value to the requester(e.g., a CPU) in a single read bus transaction, and a write cannotsupply the 64 bit data to be written to a counter in a single bustransaction. To resolve this, an alternative solution is needed.

The problem of accessing wider registers via a narrow bus is not a novelproblem. One solution is to split wide registers into separatelyaccessible sub-registers. In this approach, a write operation isimplemented to write a first set of bits to a first address, and asecond set of bits to a second address.

However, this solution is not appropriate for the hybrid counter arrayunit. This approach requires arbitration with the roll-over update logicof the control state machine, needing two (2) arbitration cycles towrite data to the memory array. If using control state machine, asdescribed in the preferred embodiment, two cycles for memory updates areneeded to store the wide value into the memory. This solution alsorequires a memory storage array with sub-words which can be writtenindependently. As a result of implementation with independent sub-words,separate parity codes have to be maintained for each sub-word, insteadof having one parity code, or ECC code, or some other memory dataprotection codes assigned per each memory word. Alternatively, aread-modify-write cycle could be implemented, which increases thelatency and response time. In this approach, data are read, partlyoverwritten and stored back to the memory. One further aspect of writingsub-words, if an overflow from one slice to the next is possible,additional constraints are to be observed to avoid race conditions.

Alternatively, to access wider registers via a narrow bus a solutionusing two staging registers and a control register can be used. Anexample of this solution is found in 6526 Complex Interface Adapter CIAby Commodore for read and write access to counters, and morespecifically for timers and time of day clocks.

In this solution, the timer is updated atomically from a latched stagingregister, by writing a first and second byte of a two-byte timer wordcontained in registers 4 and 5 (Timer A), and registers 6 and 7 (TimerB), respectively. A write of a control register 14 (CRA, for Timer A),and register 15 (CRB for Timer b) wherein bit 4 is set, forces a load ofthe 16 bit two-word latch into the counter. Alternate modes (such ascontinuous mode) of updating the counters automatically from the latchare also presented.

However, the most serious disadvantage of this solution is that itcauses excessive overhead. This solution requires to perform three writerequests to write one 16 bit value (two split one byte values plus thecontrol word), resulting in inefficient use of bus bandwidth. Efficientbus bandwidth usage is especially important in a multiprocessorenvironment.

An alternate method for updating a counter is shown for the “Time ofday” feature of the referenced part (registers 8, 9, 10, 11 containingtenths of seconds, seconds, minutes, and hours, respectively, in BCDformat). In this solution, write access to the hour register (register11) will stop operation of the clock feature. A write to the tenths ofseconds register (register 8) will resume operation of the clock.

While this approach does not cause bus inefficiency, it requires storinginternal state about whether the counter has been currently started orstopped. To apply this solution to the counter array unit, additionalstate information—if the counter is currently being written, or it is ina counter mode—has to be added to each counter. This approach thusrequires additional state to store the enable/disable mode of eachcounter, which can be significant for a big number of counters in thecounter unit. In addition, stopping the counters has undesirable effectof loosing counter events—as long a counter is in this alternate state,the counters do not count events, and all counter events happeningduring this time are lost.

In accordance with the monitoring system of the present invention, thereis provided a bus bandwidth efficient solution for memory access of widecounters (e.g., 64 bits wide) in the counter unit via a narrow (e.g., 32bit) bus. The invention provides a first staging latch containing 32bits, an array to be updated, control circuitry to deposit 32 bits ofdata from a data bus port into a staging latch addressed using aspecific register address, other control circuitry to merge 32 bit datacontained in a staging latch with 32 bit data from a data bus port, togenerate 64 bit data to write atomically, to a counter specified by aregister address.

Referring now to FIG. 8A, there is depicted a high level block diagramof a wide memory array implementation supporting memory accesses via anarrow bus in accordance with the present invention. In the preferredembodiment, the invention provides a 64 bit wide array 710 to beupdated, a staging register 730 containing 32 bits, control circuitry720 to deposit 32 bits of data from a data bus port into a stagingregister 730 addressed using a specific register address S, and controlcircuitry to merge 32 bit data contained in a staging register 730 with32 bit data from a data bus port, to generate 64 bit data to writeatomically, to a counter specified by a register address Ai.

In accordance with the present invention, a single write access to thememory array 710 by a processor or other bus master is implemented asfollows:

-   -   1. first set of bits is written to the staging register 730 by        providing as target address of a write (store) operation the        address S of the staging register 730,    -   2. then provide a subsequent set of bits (the remaining bits)        together with an array element target specification (encoded as        a plurality of the bits of the address specified in the write        transaction), in a subsequent write transaction (store).

More specifically, in reference to FIG. 8A, to perform a single writeaccess to the memory array, two write bus transactions are performed.First write bust transaction is targeting the staging register, usingthe address “S” of the staging register and writing 32 bit wide datafrom the bus into the staging register 730. The control circuitry 720generates needed control signals (such as “write” and “Select” signals)to deposit 32 bits of data from a data bus port into a staging register730.

The second write bus transaction is addressing the target memorylocation. To write data into the memory address Ai, the address “Ai” ofthe target memory location, and remaining 32 bits of the word to bewritten in the memory location Ai, are placed on the data bus. Thecontrol circuitry 720 decodes the address, generates needed controlsignals to write data into the memory array 710 (such as “write” and“select” signals), enabling writing of 32 bit data contained in astaging register 730 with 32 bit data from a data bus port, to generate64 bit data to write atomically to a memory location specified by aregister address Ai.

Referring now to FIG. 8B, a block diagram of logic needed to perform asingle read access to the memory array is depicted. In the preferredembodiment, the invention provides a 64 bit wide array 710 to be readout, a staging register 740 which is 32 bits wide, control circuitry 720to deposit 32 bits of data from the staging register 740—which isaddressed using a specific register address S1 into a data bus port, andcontrol circuitry to deposit 32 bit data from the memory array 710specified by a register address Ai which are not captured in a stagingregister 740 into a data bus port.

To perform a single read access from the memory array 710, two read bustransactions are performed. First read bust transaction is addressingthe target memory location Ai. To read data from the memory address Ai,the address “Ai” is placed on the data bus. The control circuitry 720decodes the address, generates needed control signals to read data fromthe memory array 710 (such as “read” and “select” signals). When 64 bitdata from the memory location Ai are available, one 32 bit data part arewritten in the staging register 740, and the second 32 bit data part isdriven into a 32 bit data bus port, by driving the control signals toproperly select the multiplexer 750.

The second read bus transaction is addressing the staging register 740,using the address “S1” of the staging register and reading 32 bit widedata from the staging register 740 into the data bus port. The controlcircuitry 720 decodes the address, generates needed control signals toread data from the staging register 740 and the multiplexer 750. Thus,these two transactions enable reading of any memory location in thememory array 710.

Referring now to FIGS. 9A and 9B, there are shown hardware methods forwriting and reading data elements of a memory array, such as may be usedto advantageously implement the counter unit in one exemplaryembodiment.

For example, as shown in FIG. 9A, there is depicted method steps 800 forwriting data elements to the memory array elements 710 as depicted inFIG. 8A. As shown in FIG. 9A, two steps 810 and 820 representing a firstdata bus write transaction is performed with the first step 810 of firstreceiving a write request at the staging register 730 at a predeterminedaddress, e.g., address S. Then, as depicted at step 820, a first numberof bits, e.g., 32 bits, from the narrow data bus are written to thestaging register 730 for temporary storage thereat. Then, as depicted atsteps 830 and 840 representing a second data bus write transaction, asecond write request is received at step 830 for writing the remainingdata bits on the narrow data bus to address Ai (indicating element i inthe memory array block 710 of FIG. 8A). Then, as depicted at step 840,the contents of the staging register are combined with the data from thedata bus and an atomic write operation is performed to write this datainto the memory array at a selected address corresponding to arrayelement i.

For a memory read transaction, as shown in FIG. 9B, there is depictedmethod steps 850 for reading data elements from a memory array element710 as depicted in FIG. 8B. As shown in FIG. 9B, steps 860-875 representa first data bus read transaction with a first step 860 representing thestep of receiving a read request from a memory address location, e.g.,address Ai (indicating element i in the memory array block 710 of FIG.8B). Then, at step 865, a predetermined number of bits, e.g., 64 bits,are read from array element i. Then, as depicted at step 870, one-halfof the retrieved bits, e.g., 32 bits, are first placed on the data busfrom the memory array while, at step 875, the remaining bit data, e.g.,second 32 bit data item, is stored in the staging register 740, e.g., ata predetermined address S1. Then, as depicted at steps 880 and 885representing a second data bus read transaction, a second read requestis received at step 880 for reading the data from address S1 of thestaging register. In response, at step 885, the remaining bit data,e.g., second 32 bit data item, stored at the staging register 740 isplaced on the narrow data bus for input to a requesting processor, forexample.

Referring now to FIGS. 10A, 10B, and 10C, there are shown softwaremethods for writing data elements, reading data elements, and performinga read-modify-write cycle on data elements of a memory array, such asmay be used to advantageously utilize a counter unit in one exemplaryembodiment. For example, as shown in FIG. 10A, there is depicted methodsteps 900 for writing data elements to an array element. For example asshown at step 910, FIG. 10A, a predetermined data item, e.g., 64 bits,to be written to array element i is split, for example, in half. Then,in an optional step depicted as step 920, the first half of the dataitem, e.g., 32 bits, is written to the staging register at an address S(such as staging register 730 of FIG. 8A). The second half of the dataitem, e.g., remaining 32 bits, is then written to the address Ai asindicated at step 930.

Referring now to FIG. 10B, there is depicted method steps 950 forreading data from the array elements. For example as shown at step 960,FIG. 10B, a predetermined data item, e.g., 32 bits are first receivedform the address Ai corresponding to element i in the memory array 710.Then, as depicted at step 970, the first half of the data item, e.g., 32bits, are read from the staging register from an address S1 (such asstaging register 740 of FIG. 8B). Then, as indicated at step 980, thefirst predetermined data item (e.g., 32 bits) are merged with the second32 bit data item representing the value from element i in the memoryarray.

Referring now specifically to FIG. 10C, and method 990, there is shown amethod for performing a read-modify-write cycle. In accordance with thisembodiment, staging registers S and S1 for write and read access areimplemented as a single register S, advantageously allowing efficientread-modify-write cycles to be performed.

In accordance with method 990, a read step is performed. The methodstarts with step 993. The read step 993 returns a first data portion onthe data bus corresponding to a data read request from element i, andwrite updates a staging register S with a second data portion. The writestep 996 supplies a data update portion, to be combined with said dataretained in staging register S during read step 993, and the combineddata is written to the specified element j. In one embodiment, i=j.

Advantages of the present invention are: a counter is updated atomicallyto avoid race conditions; the need for read-modify-write cycles iseliminated; the need for the ability to perform sub-word writes iseliminated; only two bus transactions are needed, i.e., the minimumnumber to transport a 64 bit datum over a 32 bit data bus.

In one optimized embodiment, the first set of bits is the high orderbits. Advantageously, this allows a set of numbers in the range from 0to 2³²-1 to be written in a single bus transactions.

This solution implements a high performance reset operation of counters,resetting a plurality of counters (i.e., initialized to the value 0).The rest is implemented as follows: (step 1) preload 0 into the staginglatch as a first set of bits; (step 2) writing 0 as remaining bits,specifying as address an address indicating the counter to beinitialized. To initialize a plurality of counters, only step 2 isrepeated for all counters, writing 0 as counter bits and specifyingcounter address of each counter to be initialized. Thus, to initialize N64 bit wide counters, only N+1 narrow 32 bit wide bus accesses arerequired. The same efficient initialization process is performed forinitializing a set of counters with any arbitrary number, with theconstraint that most significant k bits are the same, where k is theregister width. An example of such initialization is writing smallpositive or negative numbers into counters.

The same methods and apparatus can be applied to any update having afirst bus width n and a second data width m (n<m). In other embodiment,where multiple bus transactions n width have to be performed forupdating data width m, a first transaction can supply a first set ofbits, a second transaction a second set of bits, and so forth, until afinal transaction specifies a final set of remaining bits and a specificdata element.

Referring now to FIG. 11, there is shown an apparatus 1000 implementingthe hybrid counter unit for efficient monitoring of large number ofsimultaneous events for a uniprocessor or multiprocessor system, or asystem on a chip. The hybrid counter unit depicted in FIG. 11 is acombination of the individual system components as depicted in FIGS. 2,4, 5 and 8A and 8B. In one embodiment, the counter unit consists of anSRAM memory array and a set of discrete registers for implementing acounter array as described herein. Usage of SRAM for implementing eventmonitoring unit enables power-efficient implementation compact in area.This departs from traditional implementations of counter units using onlatch-based counters. That is, in prior art implementations, a number ofcounters was extremely limited due to power and area use of counterunits. Using the monitoring unit based on the memory arrayimplementation according to the invention, the power and arealimitations are alleviated, and implementation with significant numberof large counters capable of simultaneous tracking of large number ofevents is enabled.

To reduce the SRAM memory update rate, low-order bits of the countersare partitioned from the high-order bits. The high-order bits are storedin the memory array which is periodically updated, whereas the low-orderbits are implemented using latch-based discrete logic. The high-orderbits are updated when the low order bits overflow. The updating ofhigh-order bits is controlled by a state machine. The invention teachesa fast interrupt trigger architecture. In one aspect of the invention offast interrupts, there is provided a method to identify impendinginterrupts, and indicate this interrupt pending condition. As soon as acounter for which an interrupt is enabled reaches the value stored inthe interrupt threshold, if impending interrupt for this counter hasbeen identified. The interrupt is triggered when the counter, for whichinterrupt is enabled and for which impending interrupt is indicated,reaches the overflow of the low order bits of the counter. Thisarchitecture allows for fast response when interrupts trigger.

Yet another aspect of this architecture is the efficient usage of narrowbus. The architecture allows attaching the monitoring unit over a narrowbus, e.g., a bus whose width is half of the width of the counters in themonitoring unit. The present invention teaches how to enable accessingthe counters in the monitoring unit for initialization and statusaccess. The proposed method minimizes the number of stage registers, andthe number of needed bus transactions to accomplish these operations.

While the herein disclosed invention teaches usage of large counterarrays using memory arrays for counting the large number of individualevents in a computer system, such as processors, memory system, andnetwork I/Os, and is described as such in the preferred embodiment, theinvention is not limited to that particular usage. It can be equallywell applied by anybody skilled in the art to communication networksystems where large volume of packets of information is passed from portto port, and the communication quality, or other aspects ofcommunication have to be evaluated based on the number of packets whichare delivered or discarded, or based on some other information relatingto the operation of the network system.

The invention has been described herein with reference to particularexemplary embodiments. Certain alterations and modifications may beapparent to those skilled in the art, without departing from the scopeof the invention. The exemplary embodiments are meant to beillustrative, not limiting of the scope of the invention.

1. A system for monitoring performance of simultaneous occurring eventsin a single or multiprocessor computer system comprising: a hybridcounter array means for counting signals representing occurrences ofevents received from event sources having a first counter portionincluding one or more counter devices and providing a first count valuecorresponding to lower order bits of a count, and a second counterportion comprising a memory array device having addressable memorylocations, each said addressable memory location for storing a secondcount value for a respective counter device representing higher orderbits of said count, a combination of said first and corresponding secondcount values provide a number of events received at a counter device;and, an interrupt pre-indication means for providing fast interrupttrigger to a processor device when one or more count values related toan event equals a pre-determined threshold value, a means enabling oneor more of: read access or write access to both said first count valuein said first counter portion and said second count value in said secondcounter portion, said read/write access for purposes of initializing anddetermining status of said count values for a monitored event type inresponse to a processor device request.
 2. The system as claimed inclaim 1, wherein said means enabling one or more of: read access orwrite access further comprises: a bus interface means for enablingcommunication of said lower order bits and higher order bits to and fromrespective said first counter portion and second counter portion of saidhybrid counter array means.
 3. The system as claimed in claim 2, whereinsaid bus interface means comprises a data bus device of bus widthnarrower than a bit width of said count value provided as a combinationof said first and said second counter portions.
 4. The system as claimedin claim 2, wherein said first counter portion of said hybrid counterarray means comprises N counter devices, said hybrid counter array meansfurther comprising: an overflow bit means associated with eachrespective N counter device, said overflow bit means being set inresponse to reaching overflow condition; a control means operativelycoupled with each said N associated overflow bit means for monitoringeach of said N associated overflow bit means of said first counterportion and initiating incrementing a value of a corresponding saidsecond count value stored at said corresponding addressable memorylocation in said second counter portion in response to a respectiveoverflow bit being set, wherein after said initiating, said overflow bitmeans being reset.
 5. The system as claimed in claim 1, wherein eachsaid counter device comprises discrete latch elements.
 6. The system asclaimed in claim 1, wherein each said counter device comprises anincrementable register device.
 7. The system as claimed in claim 1,wherein said memory array device comprises one or more of: an SRAM, aDRAM or embedded DRAM.
 8. The system as claimed in claim 7, wherein saidmemory array device comprises a hierarchical arrangement of multiplememory blocks such that a first predetermined number of circuit means insaid second counter portion corresponds to a first memory array in saidsecond counter portion and, a second predetermined number of circuitmeans corresponds to a second memory array in said second counterportion, for each memory block in the said memory array.
 9. The systemas claimed in claim 4, wherein said control means comprises a finitestate machine, said finite state machine monitoring each respective Noverflow bits in a cycle.
 10. The system as claimed in claim 3, whereina single read access or write access to said hybrid counter array meansis performed in one or two bus transactions.
 11. The system as claimedin claim 10, wherein said means enabling one or more of: read access orwrite access to both said first count value in said first counterportion and said second count value in said second counter portionenables reading of or pre-setting of a counter value in said hybridcounter array means.
 12. The system as claimed in claim 1, wherein saidevents comprise one or more event types, a counter value in said hybridcounter array being pre-set for a particular event type.
 13. The systemas claimed in claim 11, wherein said means for enabling write access toa wide count value provided as a combination of said first and saidsecond counter portions via said narrow bit width data bus comprises: ameans for generating select control signals for controlling write accessto a memory location of said memory array device and to a counter devicein response to a processor device request; a means for storing apredetermined number of bits of data communicated via said narrow bitwidth data bus corresponding to said first counter portion to be storedat said selected counter device; and a means for storing a predeterminednumber of bits of data communicated via said narrow bit width data buscorresponding to said second counter portion to be stored at saidselected addressable memory location of said memory array device. 14.The system as claimed in claim 11, wherein said means for enabling writeaccess to a wide count value provided as a combination of said first andsaid second counter portions via said narrow bit width data buscomprises: a means for generating select control signals for controllingwrite access to a memory location of said memory array device and to acounter device in response to a processor device request; a firststaging device for receiving and storing a first predetermined number ofbits of data to be stored at said selected hybrid counter communicatedvia said data bus in a first write bus transaction; a means for mergingsaid first predetermined number of bits of data in said first stagingdevice with a second predetermined number of bits of data comprising aremaining portion of said data to be stored at said selected hybridcounter via said narrow bit width data bus being communicated in asecond write bus transaction; and a means for storing a predeterminednumber of bits of merged data corresponding to said first counterportion at said selected counter device, and storing a predeterminednumber of bits of merged data corresponding to said second counterportion to selected addressable memory location of said memory arraydevice, wherein said write access to said hybrid counter is atomic. 15.The system as claimed in claim 11, wherein said means for enabling readaccess to a wide count value provided as a combination of said first andsaid second counter portions via said narrow bit width data buscomprises: a means for generating select control signals for controllingread access to a memory location of said memory array device and to acounter device in response to a processor device request; a means forreading a predetermined number of bits of data from said selectedcounter device corresponding to said first counter portion, and drivingdata to said data bus; and a means for reading a predetermined number ofbits of data from said selected addressable memory location of saidmemory array device corresponding to said second counter portion, anddriving data to said data bus.
 16. The system as claimed in claim 14,wherein said means for enabling read access to wide count value providedas a combination of said first and said second counter portions via saidnarrow bit width data bus comprises: a means for generating selectcontrol signals for controlling read access to a memory location of saidmemory array device and to a counter device in response to a processordevice request; a second staging device for receiving and storing afirst predetermined number of bits of data read from said selectedaddressable memory location of said memory array device, said receivingand storing performed in a first read bus transaction; a means formerging data corresponding to said first counter portion at saidselected counter device with the second predetermined number of bits ofdata read from said selected addressable memory location of said memoryarray device, and driving data to said narrow bit width data bus inresponse to processor device request in a first read bus transaction;and a means for driving data stored in said second staging register tosaid narrow bit width data bus in a second read bus transaction,comprising a remaining portion of said data from said selected hybridcounter.
 17. The system as claimed in claim 16, wherein said first andsecond staging device comprises a register device addressable by saidprocessor device.
 18. The system as claimed in claim 4, said interruptpre-indication means further comprising: a means for comparing anincremented second count value against a pre-determined threshold value;an interrupt arming device associated with each respective counterdevice for enabling fast interrupt indication, said interrupt armingdevice being set in response to said incremented second count valuebeing equal to said pre-determined threshold value; and, a meansimplementing logic coupled to an output of said interrupt arming deviceand an output of said overflow bit means for asserting an interruptsignal when an overflow bit means corresponding to a counter device isset, and said interrupt arming device associated with said counterdevice is set, wherein said interrupt signal is asserted independent ofa state of said control means.
 19. The system as claimed in claim 18,wherein said pre-determined threshold value equals a desired interruptthreshold value decremented by one (1).
 20. The system as claimed inclaim 18, further comprising means for tracking which counter devicecauses assertion of said interrupt signal.
 21. The system as claimed inclaim 18, further comprising one or more configuration bit meansassigned to a respective counter device for defining a mode of operationfor said counter device, wherein one mode of operation comprises aninterrupt indication mode.
 22. The system as claimed in claim 18,further comprising: an incrementing register device for receiving asecond count value contained in an addressable memory location inresponse to a corresponding overflow bit being set in an associatedcounter device; logic means for incrementing said second count value insaid incrementing register device; and control logic executed by saidlogic means to store back said incremented second count value to saidassociated addressable memory location.
 23. A method for monitoringperformance of simultaneous occurring events in a single ormultiprocessor computer system comprising: counting signals representingoccurrences of events from event sources at a hybrid counter arraydevice having a first counter portion including one or more counterdevices, and providing a first count value corresponding to lower orderbits of a count, said hybrid counter array device having a secondcounter portion comprising a memory array device having addressablememory locations, each said addressable memory location for storing asecond count value for a respective counter device representing higherorder bits of said count, a combination of said first and correspondingsecond count values provide number of events received at a counterdevice; enabling one or more of: read access or write access to bothsaid first count value in said first counter portion and said secondcount value in said second counter portion, said read/write access forpurposes of initializing and determining status of said first and secondcount values in respective first and second counter portions for amonitored event type in response to a processor device request; and,providing a fast interrupt trigger to a processor device when one ormore count values related to an event type equals a pre-determinedthreshold value.
 24. The method as claimed in claim 23, wherein saidenabling one or more of: read access or write access comprises:communicating, via a bus interface device, said lower order bits andhigher order bits to and from respective said first counter portion andsecond counter portion of said hybrid counter array device, said businterface device including a data bus device of bus width equal to ornarrower than a bit width of said addressable memory location at saidmemory array device.
 25. The method as claimed in claim 24, wherein saidfirst counter portion of said hybrid counter array means comprisescounter devices, said method further comprising: setting an overflow bitmeans associated with each respective counter device in response to anassociated counter device reaching an overflow condition; and,monitoring, by a control means, each of said associated overflow bitmeans of said first counter portion, initiating incrementing a value ofa corresponding said second count value stored at said correspondingaddressable memory location in said second counter portion in responseto a respective overflow bit being set, and resetting overflow bit meansafter said initiating.
 26. The method as claimed in claim 25, whereinsaid memory array device comprises one or more of: an SRAM, a DRAM orembedded DRAM.
 27. The method as claimed in claim 26, furthercomprising: hierarchically arranging said memory array device intomultiple memory blocks such that a first predetermined number ofcounters in said first counter portion corresponds to a first memoryarray in said second counter portion and, a second predetermined numberof counters in said first counter portion corresponds to a second memoryarray in said second counter portion, for each memory block in the saidmemory array.
 28. The method as claimed in claim 25, wherein saidmonitoring by said control means comprises: cycling through each of saidassociated overflow bit means of said first counter portion to determinea state of said associated overflow bit means.
 29. The method as claimedin claim 25, further comprising: performing a single read access orwrite access to a count value in said hybrid counter array device in oneor two bus transactions.
 30. The method as claimed in claim 29, whereinsaid count value is a wide count value provided as a combination of saidfirst and said second counter portions, said means for performing writeaccess to said wide count value via said narrower bit width data buscomprises: generating select control signals for controlling writeaccess to a selected addressable memory location of said memory arraydevice in response to a processor device request; receiving and storinga predetermined number of bits of data communicated via said data buscorresponding to said first counter portion to be stored at saidselected counter device; and receiving and storing a predeterminednumber of bits of data communicated via said data bus corresponding tosaid second counter portion to be stored at said selected addressablememory location of said memory array device.
 31. The method as claimedin claim 29, wherein said count value is a wide count value provided asa combination of said first and said second counter portions, said meansfor performing write access to said wide count value via said narrow bitwidth data bus comprises: generating select control signals forcontrolling write access to a memory location of said memory arraydevice and to a counter device in response to a processor devicerequest; receiving and storing a first predetermined number of bits ofdata to be stored at selected hybrid counter device communicated viasaid data bus in a first write bus transaction to a first stagingdevice; receiving a second predetermined number of bits of datacomprising a remaining portion of said data to be stored at saidselected hybrid counter via said narrow data bus being subsequentlycommunicated in a second write bus transaction, and merging said firstpredetermined number of bits of data in said first staging device withsaid second predetermined number of bits of said data communicated viasaid data bus; and storing a predetermined number of bits of merged datacorresponding to said first counter portion at said selected counterdevice, and storing a predetermined number of bits of merged datacorresponding to said second counter portion to selected addressablememory location of said memory array device, wherein said write accessto said hybrid counter is atomic.
 32. The method as claimed in claim 30,further comprising: generating control signals for controlling readaccess of a selected addressable memory location of said memory arraydevice and to a counter device in response to a processor devicerequest; reading a predetermined number of bits of data from saidselected counter device corresponding to said first counter portion, anddriving data to said data bus; and reading a predetermined number ofbits of data from said selected addressable memory location of saidmemory array device corresponding to said second counter portion, anddriving data to said data bus.
 33. The method as claimed in claim 31,further comprising: generating control signals for controlling readaccess to a memory location of said memory array device and to a counterdevice in response to a processor device request; receiving and storinga first predetermined number of bits of data read from said selectedaddressable memory location of said memory array device to a secondstaging device, said receiving and storing performed in a first read bustransaction; merging data corresponding to said first counter portion atsaid selected counter device with the second predetermined number ofbits of data read from said selected addressable memory location of saidmemory array device, and driving data to said narrow data bus inresponse to processor device request, said merging and driving performedin a first read bus transaction; and driving data stored in said secondstaging register to said narrow data bus in a second read bustransaction, comprising a remaining portion of said data from saidselected hybrid counter.
 34. The method as claimed in claim 25, whereinsaid providing a fast interrupt trigger to a processor device comprises:comparing a second count value against said pre-determined thresholdvalue; setting an interrupt arming device associated with a respectivecounter device for enabling fast interrupt indication in response to anassociated second count value being equal to a pre-determined thresholdvalue; and, asserting an interrupt signal when said overflow bit meanscorresponding to a counter device is set and said interrupt armingdevice for said counter device is set, wherein said interrupt signal isasserted independent of a state of said control means.
 35. The method asclaimed in claim 34, wherein said pre-determined threshold value equalsa desired interrupt threshold value decremented by one (1).
 36. Themethod as claimed in claim 34, further comprising: tracking whichcounter device causes assertion of said interrupt signal.
 37. The methodas claimed in claim 34, further comprising: defining a mode of operationfor each said counter devices, said defining including assigning one ormore configuration bits to each respective counter device, one of saidconfiguration bits indicating an interrupt indication mode, one or moreof said configuration bits selecting one of several events for counting,and one or more of said configuration bits indicating an event type. 38.The method as claimed in claim 33, wherein said initiating incrementinga value of a corresponding said second count value comprises: receiving,at a register device, said second count value contained in saidcorresponding addressable memory location; incrementing said secondcount value in said register device; and, loading said incrementedsecond count value back in said associated addressable memory location.